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1006 IP
551
0.118
UMC 28nm HPC process standard synchronous HVT periphery high density single port low power SRAM memory compiler with row redundancy
UMC 28nm HPC process standard synchronous HVT periphery high density single port low power SRAM memory compiler with row redundancy...
552
0.118
UMC 28nm HPC process standard synchronous LVT periphery high density single port low power SRAM memory compiler with row redundancy
UMC 28nm HPC process standard synchronous LVT periphery high density single port low power SRAM memory compiler with row redundancy...
553
0.118
UMC 28nm HPC process synchronous HVT periphery high density single port SRAM memory compiler.
UMC 28nm HPC process synchronous HVT periphery high density single port SRAM memory compiler....
554
0.118
UMC 28nm HPC process synchronous LVT periphery high density single port SRAM memory compiler.
UMC 28nm HPC process synchronous LVT periphery high density single port SRAM memory compiler....
555
0.118
UMC 28nm HPC process Two Port Register File
UMC 28nm HPC process Two Port Register File...
556
0.118
UMC 28nm HPC process Two Port Register File with Bank2
UMC 28nm HPC process Two Port Register File with Bank2...
557
0.118
UMC 28nm HPC process Two Port Register File with LVT and Bank2
UMC 28nm HPC process Two Port Register File with LVT and Bank2...
558
0.118
UMC 28nm HPC process Two Port Register File with LVT and Bank4
UMC 28nm HPC process Two Port Register File with LVT and Bank4...
559
0.118
UMC 28nm HPC process Two Port Register File with peri LVT
UMC 28nm HPC process Two Port Register File with peri LVT...
560
0.118
UMC 28nm HPC Process Ultra High Speed One Port Register File Memory Compiler
UMC 28nm HPC Process Ultra High Speed One Port Register File Memory Compiler...
561
0.118
UMC 28nm HPC Process Ultra High Speed One Port Register File Memory Compiler with periphery LVT
UMC 28nm HPC Process Ultra High Speed One Port Register File Memory Compiler with periphery LVT...
562
0.118
UMC 28nm HPC Process Ultra High Speed Single-Port SRAM memory compiler
UMC 28nm HPC Process Ultra High Speed Single-Port SRAM memory compiler...
563
0.118
UMC 28nm HPC Process Ultra High Speed Single-Port SRAM Memory Compiler
UMC 28nm HPC Process Ultra High Speed Single-Port SRAM Memory Compiler...
564
0.118
UMC 28nm HPM process standard synchronous high density single port SRAM memory compiler
UMC 28nm HPM process standard synchronous high density single port SRAM memory compiler...
565
0.118
UMC 28nm HPM process synchronous LVT preiphery high density single port SRAM memory compiler with Row and 2 Column Repair
UMC 28nm HPM process synchronous LVT preiphery high density single port SRAM memory compiler with Row and 2 Column Repair...
566
0.118
UMC 28nm HPM ultra high speed register compiler
UMC 28nm HPM ultra high speed register compiler...
567
0.118
UMC 28nm Logic process standard synchronous LVT periphery high density single port SRAM memory compiler.
UMC 28nm Logic process standard synchronous LVT periphery high density single port SRAM memory compiler....
568
0.118
UMC 28nm Logic process standard synchronous LVT periphery high density single port SRAM memory compiler.
UMC 28nm Logic process standard synchronous LVT periphery high density single port SRAM memory compiler....
569
0.118
UMC 28nm Logic process standard synchronous RVT periphery high density single port SRAM memory compiler with row redundancy.
UMC 28nm Logic process standard synchronous RVT periphery high density single port SRAM memory compiler with row redundancy....
570
0.118
UMC 28nm Logic process standard synchronous RVT periphery high density single port SRAM memory compiler.
UMC 28nm Logic process standard synchronous RVT periphery high density single port SRAM memory compiler....
571
0.118
UMC 40nm embedded high voltage (eHV) low power Process standard synchronous high density single port register file SRAM memory compiler.
UMC 40nm embedded high voltage (eHV) low power Process standard synchronous high density single port register file SRAM memory compiler....
572
0.118
UMC 40nm Logic process standard Synchronous High Density Two Port Register File SRAM memory compiler.
UMC 40nm Logic process standard Synchronous High Density Two Port Register File SRAM memory compiler....
573
0.118
UMC 40nm Low Power Process , Two Port Register File with dual power rail
UMC 40nm Low Power Process , Two Port Register File with dual power rail...
574
0.118
UMC 40nm Low Power Process Dual-Port SRAM compiler with dual power rail
UMC 40nm Low Power Process Dual-Port SRAM compiler with dual power rail...
575
0.118
UMC 40nm Low Power Process One Port Register File wit 213 cell
UMC 40nm Low Power Process One Port Register File wit 213 cell...
576
0.118
UMC 40nm Low Power Process One Port Register File with 213 cell
UMC 40nm Low Power Process One Port Register File with 213 cell...
577
0.118
UMC 40nm Low Power Process PG SP-SRAM with Row redundancy for 213 bit cell
UMC 40nm Low Power Process PG SP-SRAM with Row redundancy for 213 bit cell...
578
0.118
UMC 40nm Low Power Process Single-Port SRAM 213cell with power gating
UMC 40nm Low Power Process Single-Port SRAM 213cell with power gating...
579
0.118
UMC 40nm Low Power Process Single-Port SRAM for dual power rail
UMC 40nm Low Power Process Single-Port SRAM for dual power rail...
580
0.118
UMC 40nm Low Power Process SP-SRAM memory compiler with row redundancy and 213 bit cell
UMC 40nm Low Power Process SP-SRAM memory compiler with row redundancy and 213 bit cell...
581
0.118
UMC 40nm Low Power Process SP-SRAM with 213 bit cell
UMC 40nm Low Power Process SP-SRAM with 213 bit cell...
582
0.118
UMC 40nm low power process standard synchronous one port register file SRAM memory compiler with HVT peripheral.
UMC 40nm low power process standard synchronous one port register file SRAM memory compiler with HVT peripheral....
583
0.118
UMC 40nm low power process standard synchronous one port register file SRAM memory compiler with LVT peripheral.
UMC 40nm low power process standard synchronous one port register file SRAM memory compiler with LVT peripheral....
584
0.118
UMC 40nm Low Power Process Ultra High Speed One Port Register File memory compiler with dual rail
UMC 40nm Low Power Process Ultra High Speed One Port Register File memory compiler with dual rail...
585
0.118
UMC 40NM Low-K Low Power synchronous Feature Dual Port SRAM memory compiler
UMC 40NM Low-K Low Power synchronous Feature Dual Port SRAM memory compiler...
586
0.118
UMC 40NM Low-K Low Power synchronous Feature Dual Port SRAM memory compiler
UMC 40NM Low-K Low Power synchronous Feature Dual Port SRAM memory compiler...
587
0.118
UMC 40nm Low-K Low Power synchronous Feature Dual Port SRAM memory compiler
UMC 40nm Low-K Low Power synchronous Feature Dual Port SRAM memory compiler...
588
0.118
UMC 40nm LP Dual Port SRAM compiler with Sleep/Retention mode
UMC 40nm LP Dual Port SRAM compiler with Sleep/Retention mode...
589
0.118
UMC 40nm LP Logic Process Dual-Port SRAM Memory Compiler with LVT peripheral
UMC 40nm LP Logic Process Dual-Port SRAM Memory Compiler with LVT peripheral...
590
0.118
UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy
UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy...
591
0.118
UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy and LVT peripheral
UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy and LVT peripheral...
592
0.118
UMC 40nm LP Logic Process one-port register file for area optimize with HVT peripheral
UMC 40nm LP Logic Process one-port register file for area optimize with HVT peripheral...
593
0.118
UMC 40nm LP Logic Process one-port register file for area optimize with LVT peripheral
UMC 40nm LP Logic Process one-port register file for area optimize with LVT peripheral...
594
0.118
UMC 40nm LP Logic Process Single Port SRAM memory compiler using 213 bit -cell with peri-HVT
UMC 40nm LP Logic Process Single Port SRAM memory compiler using 213 bit -cell with peri-HVT...
595
0.118
UMC 40nm LP Logic Process Single Port SRAM Memory Compiler using 213 bit-cell with Peri-LVT
UMC 40nm LP Logic Process Single Port SRAM Memory Compiler using 213 bit-cell with Peri-LVT...
596
0.118
UMC 40nm LP Logic Process standard synchronous high density dual port SRAM memory compiler with LVT
UMC 40nm LP Logic Process standard synchronous high density dual port SRAM memory compiler with LVT...
597
0.118
UMC 40nm LP Logic Process standard synchronous high density dual port SRAM memory compiler with ROW redundancy with LVt peripheral
UMC 40nm LP Logic Process standard synchronous high density dual port SRAM memory compiler with ROW redundancy with LVt peripheral...
598
0.118
UMC 40nm LP Logic Process TCAM with LVT peripheral memory compiler
UMC 40nm LP Logic Process TCAM with LVT peripheral memory compiler...
599
0.118
UMC 40nm LP Logic Process Two-Port Register File with LVT Peripheral Memory Compiler
UMC 40nm LP Logic Process Two-Port Register File with LVT Peripheral Memory Compiler...
600
0.118
UMC 40nm LP Logic Process ULL Single Port SRAM Memory Compiler using 213 bit-cell with peri-HVT
UMC 40nm LP Logic Process ULL Single Port SRAM Memory Compiler using 213 bit-cell with peri-HVT...
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