Design & Reuse
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arrow Embedded Memories (989)
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989 IP
551
0.118
UMC 40nm Low Power Process Single-Port SRAM for dual power rail
UMC 40nm Low Power Process Single-Port SRAM for dual power rail...
552
0.118
UMC 40nm Low Power Process SP-SRAM memory compiler with row redundancy and 213 bit cell
UMC 40nm Low Power Process SP-SRAM memory compiler with row redundancy and 213 bit cell...
553
0.118
UMC 40nm Low Power Process SP-SRAM with 213 bit cell
UMC 40nm Low Power Process SP-SRAM with 213 bit cell...
554
0.118
UMC 40nm low power process standard synchronous one port register file SRAM memory compiler with HVT peripheral.
UMC 40nm low power process standard synchronous one port register file SRAM memory compiler with HVT peripheral....
555
0.118
UMC 40nm low power process standard synchronous one port register file SRAM memory compiler with LVT peripheral.
UMC 40nm low power process standard synchronous one port register file SRAM memory compiler with LVT peripheral....
556
0.118
UMC 40nm Low Power Process Ultra High Speed One Port Register File memory compiler with dual rail
UMC 40nm Low Power Process Ultra High Speed One Port Register File memory compiler with dual rail...
557
0.118
UMC 40NM Low-K Low Power synchronous Feature Dual Port SRAM memory compiler
UMC 40NM Low-K Low Power synchronous Feature Dual Port SRAM memory compiler...
558
0.118
UMC 40NM Low-K Low Power synchronous Feature Dual Port SRAM memory compiler
UMC 40NM Low-K Low Power synchronous Feature Dual Port SRAM memory compiler...
559
0.118
UMC 40nm Low-K Low Power synchronous Feature Dual Port SRAM memory compiler
UMC 40nm Low-K Low Power synchronous Feature Dual Port SRAM memory compiler...
560
0.118
UMC 40nm LP Dual Port SRAM compiler with Sleep/Retention mode
UMC 40nm LP Dual Port SRAM compiler with Sleep/Retention mode...
561
0.118
UMC 40nm LP Logic Process Dual-Port SRAM Memory Compiler with LVT peripheral
UMC 40nm LP Logic Process Dual-Port SRAM Memory Compiler with LVT peripheral...
562
0.118
UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy
UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy...
563
0.118
UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy and LVT peripheral
UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy and LVT peripheral...
564
0.118
UMC 40nm LP Logic Process one-port register file for area optimize with HVT peripheral
UMC 40nm LP Logic Process one-port register file for area optimize with HVT peripheral...
565
0.118
UMC 40nm LP Logic Process one-port register file for area optimize with LVT peripheral
UMC 40nm LP Logic Process one-port register file for area optimize with LVT peripheral...
566
0.118
UMC 40nm LP Logic Process Single Port SRAM memory compiler using 213 bit -cell with peri-HVT
UMC 40nm LP Logic Process Single Port SRAM memory compiler using 213 bit -cell with peri-HVT...
567
0.118
UMC 40nm LP Logic Process Single Port SRAM Memory Compiler using 213 bit-cell with Peri-LVT
UMC 40nm LP Logic Process Single Port SRAM Memory Compiler using 213 bit-cell with Peri-LVT...
568
0.118
UMC 40nm LP Logic Process standard synchronous high density dual port SRAM memory compiler with LVT
UMC 40nm LP Logic Process standard synchronous high density dual port SRAM memory compiler with LVT...
569
0.118
UMC 40nm LP Logic Process standard synchronous high density dual port SRAM memory compiler with ROW redundancy with LVt peripheral
UMC 40nm LP Logic Process standard synchronous high density dual port SRAM memory compiler with ROW redundancy with LVt peripheral...
570
0.118
UMC 40nm LP Logic Process TCAM with LVT peripheral memory compiler
UMC 40nm LP Logic Process TCAM with LVT peripheral memory compiler...
571
0.118
UMC 40nm LP Logic Process Two-Port Register File with LVT Peripheral Memory Compiler
UMC 40nm LP Logic Process Two-Port Register File with LVT Peripheral Memory Compiler...
572
0.118
UMC 40nm LP Logic Process ULL Single Port SRAM Memory Compiler using 213 bit-cell with peri-HVT
UMC 40nm LP Logic Process ULL Single Port SRAM Memory Compiler using 213 bit-cell with peri-HVT...
573
0.118
UMC 40nm LP Logic Process ULL Single Port SRAM Memory Compiler using 213 bit-cell with peri-LVT
UMC 40nm LP Logic Process ULL Single Port SRAM Memory Compiler using 213 bit-cell with peri-LVT...
574
0.118
UMC 40nm LP Logic Process Ultra High Speed One-Port Register File_x005F_x005F_x005F_x005F_x005F_x000D_
UMC 40nm LP Logic Process Ultra High Speed One-Port Register File...
575
0.118
UMC 40nm LP LowK Logic Process ULL Dual-Port SRAM Memory Compiler with Peri-LVT
UMC 40nm LP LowK Logic Process ULL Dual-Port SRAM Memory Compiler with Peri-LVT...
576
0.118
UMC 40nm LP process standard synchronous high density TCAM memory compiler.
UMC 40nm LP process standard synchronous high density TCAM memory compiler....
577
0.118
UMC 40nm LP process synchronous high density (0.213LPHVT cell) single port SRAM compiler with row redundancy.
UMC 40nm LP process synchronous high density (0.213LPHVT cell) single port SRAM compiler with row redundancy....
578
0.118
UMC 40nm LP with power gating & peri-HVT 1PRF
UMC 40nm LP with power gating & peri-HVT 1PRF...
579
0.118
UMC 40nm uLP Logic Process 1-Port Register File with Peri-HVT
UMC 40nm uLP Logic Process 1-Port Register File with Peri-HVT...
580
0.118
UMC 40nm uLP process ULL One Port Register File memory compiler
UMC 40nm uLP process ULL One Port Register File memory compiler...
581
0.118
UMC 40nm uLP process ULL Single-Port SRAM
UMC 40nm uLP process ULL Single-Port SRAM...
582
0.118
UMC 40nm uLP process ULL Via1 ROM compiler
UMC 40nm uLP process ULL Via1 ROM compiler...
583
0.118
UMC 40nm ultra low power via1 ROM complier
UMC 40nm ultra low power via1 ROM complier...
584
0.118
UMC 55nm eFlash eFlash Dual-Port SRAM Memory Compiler
UMC 55nm eFlash eFlash Dual-Port SRAM Memory Compiler...
585
0.118
UMC 55nm eFlash peocess One Port Register File memory compiler_x005F_x005F_x005F_x005F_x005F_x000D_
UMC 55nm eFlash peocess One Port Register File memory compiler...
586
0.118
UMC 55nm eflash process , Two Port Register File memory compiler
UMC 55nm eflash process , Two Port Register File memory compiler...
587
0.118
UMC 55nm EFLASH Process Dual-Port SRAM Memory Compiler
UMC 55nm EFLASH Process Dual-Port SRAM Memory Compiler...
588
0.118
UMC 55nm eFlash Process Dual-Port SRAM with Row redundancy
UMC 55nm eFlash Process Dual-Port SRAM with Row redundancy...
589
0.118
UMC 55nm eFlash process process synchronous low power feature RVT peripheral high density single port SRAM compiler.
UMC 55nm eFlash process process synchronous low power feature RVT peripheral high density single port SRAM compiler....
590
0.118
UMC 55nm eFlash process process ULL ROM Memory Compiler
UMC 55nm eFlash process process ULL ROM Memory Compiler...
591
0.118
UMC 55nm eFlash process synchronous low power feature RVT peripheral high density single port SRAM compiler with row redundancy.
UMC 55nm eFlash process synchronous low power feature RVT peripheral high density single port SRAM compiler with row redundancy....
592
0.118
UMC 55nm EFLASH Process Two Port Register File
UMC 55nm EFLASH Process Two Port Register File...
593
0.118
UMC 55nm EFLASH Process ULL One Port Register File
UMC 55nm EFLASH Process ULL One Port Register File...
594
0.118
UMC 55nm EFLASH Process Via ROM Memory complier
UMC 55nm EFLASH Process Via ROM Memory complier...
595
0.118
UMC 55nm EFLASH Processy Single-Port SRAM with row repair Memory complier
UMC 55nm EFLASH Processy Single-Port SRAM with row repair Memory complier...
596
0.118
UMC 55nm eFlash Single-Port SRAM memory compiler
UMC 55nm eFlash Single-Port SRAM memory compiler...
597
0.118
UMC 55nm eflash/ulp process standard synchronous high density single port SRAM memory compiler.
UMC 55nm eflash/ulp process standard synchronous high density single port SRAM memory compiler....
598
0.118
UMC 55nm eHV process ; Single-Port SRAM compiler with Row redundancy
UMC 55nm eHV process ; Single-Port SRAM compiler with Row redundancy...
599
0.118
UMC 55nm eHV Process Single Port SRAM Memory Compiler with Peripheral H/LVT using 277 bit-cell
UMC 55nm eHV Process Single Port SRAM Memory Compiler with Peripheral H/LVT using 277 bit-cell...
600
0.118
UMC 55nm eHV Process Single Port SRAM with row redundancy for 277cell
UMC 55nm eHV Process Single Port SRAM with row redundancy for 277cell...